1. Field of the Invention
The present invention relates to a portable semiconductor memory device and particularly, to a memory device which allows access to an internal memory when connected to terminal equipment through a connector.
2. Description of the Related Art
FIG. 7 shows the configuration of a circuit of a conventional portable semiconductor memory device. The memory, device has as an internal memory a static RAM 1, to which a battery 4 is connected through an internal power line 8 for supplying a voltage, a reverse charge preventing diode 6 and a current limiting resistor 5. A power input line 7 is connected to the internal power line 8 through a power control circuit 3 and to a connector 35. A buffer circuit 2 is connected to the internal power line 8, RAM 1, and the connector 35. The buffer circuit is connected to the connector 35 by an address bus 10, a control bus 11 and a data bus 12. The power control circuit 3 and the buffer circuit 2 are connected to each other by a control line 9. In the drawing, reference numeral 33 denotes a pull-up resistor connected between the internal power line 8 and the control bus 11.
When the memory device having the above-mentioned configuration is used, it is mounted on terminal equipment (not shown) through the connector 35. If a voltage greater than a defined value is applied to the power input line 7, the power control circuit 3 connects the power input line 7 and the internal power line 8 and sends a high level control signal to the buffer circuit 2 over the control line 9. This operation causes the voltage to be supplied to the RAM 1 and the buffer circuit 2 over the internal power line 8. The high level control signal brings the buffer circuit 2 into an enable (operable) state. In other words, the terminal equipment can get access to the RAM 1, i.e, reading from or writing in the RAM 1, over the address bus 10, the control bus 11 and the data bus 12. During this operation, since the potential of the internal power line 8 is set to a value higher than the potential of the positive side of the battery 4, the current of the battery 4 is not consumed.
When access to the RAM 1 is completed, and when a given power voltage is not applied to the input line 7, the power control circuit 3 detects that the voltage of the power input line 7 is less than the defined value and disconnects the power input line 7 from the internal power line 8 and sends a low level control signal to the buffer circuit 2 over the control line 9. The control signal brings the buffer circuit 2 into a disable (non-operating) state wherein any access to the RAM 1 is prohibited.
In this state, although no voltage is supplied to the RAM 1 through the power input line 7, the voltage of the battery 4 is supplied through the resistor 5 and the diode 6. Even if the memory device is removed from the terminal equipment, therefore, the data stored in the RAM 1 is not erased or lost but in the memory device.
However, since the connection between the memory device and the terminal equipment is effected through the connector 35 having many contact points, when foreign substances adhere to the contact points, when a contact point is deformed or broken or when the memory device is attached to the terminal equipment at an angle, in some cases unstable or poor contacts or contact errors occur. If writing to or reading from a given address area of the memory device is performed from the terminal equipment in these circumstances, there is danger of a malfunction. In particular, there is a danger of erasing the valuable data stored in the RAM 1. It is impossible to perfectly connect the connector 35 to accurately combine the memory device with the terminal equipment.